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3.3 V, 50 Mbps to 4.25 Gbps, Single-Loop, Laser Diode Driver ADN2873
FEATURES
SFP/SFF and SFF-8472 MSA compliant SFP reference design available 50 Mbps to 4.25 Gbps operation Automatic average power control Typical 60 ps output rise/fall time VCSEL, DFB, and FP laser support Bias current range: from 2 mA to 100 mA Modulation current range: from 5 mA to 90 mA Laser fail alarm and automatic laser shutdown (ALS) Bias and modulation current monitoring Voltage setpoint control Resistor setpoint control 3.3 V supply 24-lead 4 mm x 4 mm LFCSP Pin compatible with ADN2870
GENERAL DESCRIPTION
Like the ADN2870, the ADN2873 laser diode driver (LDD) is designed for advanced SFP and SFF modules, using SFF-8472 digital diagnostics. The ADN2873 supports NRZ data transmission operation from 50 Mbps up to 4.25 Gbps. With a new alarm scheme, this device avoids the shutdown issue caused by the system transient generated from various lasers. The ADN2873 monitors the laser bias and modulation currents and it provides fail alarms and ALS. Using setup voltages of a microcontroller DAC or a trimmable resistor voltage divider, the ADN2873 can set up a laser optical average output power and extinction ratio. The optical average power control loop consists of an optical feedback from a photodiode, the comparator, and a status holder. The ADN2873 works easily with the Analog Devices, Inc., ADuC7019/ADuC702x family of MicroConverter(R) devices and with the ADN289x family of limiting amplifiers to make a complete SFP/SFF transceiver chipset solution. The ADN2873 is pin compatible with the ADN2870 dual-loop LDD, allowing the same design to work with either device. For dual-loop control applications, refer to the ADN2870 data sheet. The product is available in a space-saving 24-lead, 4 mm x 4 mm LFCSP specified over the -40C to +85C temperature range. Figure 1 shows an application diagram of the voltage setpoint control with single-ended laser interface. Figure 36 shows a differential laser interface.
APPLICATIONS
1x/2x/4x Fibre Channel SFP/SFF modules Multirate OC3 to OC48-FEC SFP/SFF modules LX-4 modules DWDM/CWDM laser transmitters HDTV (SMPTE family) laser transmitters
APPLICATIONS DIAGRAM
VCC Tx_DISABLE Tx_FAULT VCC MPD ANALOG DEVICES MICROCONTROLLER DAC ADC 1k GND DAC ERREF ERSET 1k GND VCC GND 1k GND 470 GND
07493-001
VCC
VCC L VCC LASER
FAIL
ALS
IMODN
R IMODP
DATAP DATAN VCC IBIAS x100 IMOD CCBIAS RZ
PAVSET PAVREF RPAV CONTROL 100
ADN2873
IBMON IMMON PAVCAP GND NC
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
ADN2873 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Applications Diagram ...................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 SFP Timing Specifications........................................................... 5 Absolute Maximum Ratings............................................................ 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 8 Single-Ended Output ................................................................... 8 Differential Output ....................................................................... 9 Performance Characteristics ..................................................... 10 Optical Waveforms ......................................................................... 12 Theory of Operation ...................................................................... 13 Laser Control .............................................................................. 13 Control Methods ........................................................................ 13 Voltage Setpoint Calibration ..................................................... 13 Resistor Setpoint Calibration .................................................... 15 IMPD Monitoring .......................................................................... 15 Loop Bandwidth Selection ........................................................ 16 Power Consumption .................................................................. 16 Automatic Laser Shutdown (TX_Disable) .............................. 16 Bias and Modulation Monitor Currents.................................. 16 IBIAS Pin ..................................................................................... 16 Data Inputs .................................................................................. 17 Laser Diode Interfacing ............................................................. 17 Alarms.......................................................................................... 18 Outline Dimensions ....................................................................... 19 Ordering Guide .......................................................................... 19
REVISION HISTORY
6/08--Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADN2873 SPECIFICATIONS
VCC = 3.0 V to 3.6 V. All specifications TMIN to TMAX1, unless otherwise noted. Typical values are specified at 25C. Table 1.
Parameter LASER BIAS CURRENT (IBIAS) Output Current IBIAS Compliance Voltage IBIAS when ALS Is High MODULATION CURRENT (IMODP, IMODN)2 Output Current IMOD Compliance Voltage IMOD when ALS Is High Rise Time Single-Ended Output2, 3 Fall Time Single-Ended Output2, 3 Random Jitter Single-Ended Output2, 3 Deterministic Jitter Single-Ended Output3, 4 Pulse Width Distortion2, 3 Single-Ended Output Rise Time Differential Output3, 5 Fall Time Differential Output3, 5 Random Jitter Differential Output3, 5 Deterministic Jitter Differential Output3, 6 Pulse Width Distortion Differential Output3, 5 Rise Time Differential Output3, 5 Fall Time Differential Output3, 5 Random Jitter Differential Output3, 5 Deterministic Jitter Differential Output3, 7 Pulse Width Distortion Differential Output3, 5 AVERAGE POWER SET (PAVSET) Pin Capacitance Voltage Photodiode Monitor Current (Average Current) EXTINCTION RATIO SET INPUT (ERSET) Resistance Range AVERAGE POWER REFERENCE VOLTAGE INPUT (PAVREF) Voltage Range Photodiode Monitor Current (Average Current) EXTINCTION RATIO REFERENCE VOLTAGE INPUT (ERREF) Voltage Range ERREF Voltage to IMOD Gain DATA INPUTS (DATAP, DATAN)8 Input Voltage Swing (Differential) Input Impedance (Single-Ended) LOGIC INPUTS (ALS) VIH VIL ALARM OUTPUT (FAIL)9 VOFF VON Min 2 1.2 Typ Max 100 VCC 0.1 90 VCC 0.1 104 96 1.1 35 30 Unit mA V mA mA V mA ps ps ps (rms) ps ps ps ps ps (rms) ps ps ps ps ps (rms) ps ps pF V A k k V A V mA/V V p-p V V V V Voltage required at FAIL for IBIAS and IMOD to turn off when FAIL asserted Voltage required at FAIL for IBIAS and IMOD to stay on when FAIL asserted Conditions/Comments
5 1.5 60 60 0.8 19 21 47.1 46 0.64 12 2.1 56 55 0.61 17 1.6
5 mA < IMOD < 90 mA 5 mA < IMOD < 90 mA 5 mA < IMOD < 90 mA 5 mA < IMOD < 90 mA 20 mA < IMOD < 90 mA 20 mA < IMOD < 90 mA 5 mA < IMOD < 30 mA 5 mA < IMOD < 30 mA 5 mA < IMOD < 30 mA 5 mA < IMOD < 30 mA 5 mA < IMOD < 30 mA 5 mA < IMOD < 90 mA 5 mA < IMOD < 90 mA 5 mA < IMOD < 90 mA 5 mA < IMOD < 90 mA 5 mA < IMOD < 90 mA
1.1 50 1.5 0.99 0.07 70 0.05
1.2
80 1.3 1200 25 1.01 1 1000 0.9
Resistor setpoint mode Resistor setpoint mode Voltage setpoint mode Voltage setpoint mode (RPAV fixed at 1 k) Voltage setpoint mode (RPAV fixed at 1 k) Voltage setpoint mode (RERSET fixed at 1 k)
1
100 0.4 50 2 0.8 >1.8 <1.3 2.4
AC-coupled
Rev. 0 | Page 3 of 20
ADN2873
Parameter IBMON, IMMON DIVISION RATIO IBIAS/IBMON3 IBIAS/IBMON3 IBIAS/IBMON3 IBIAS/IBMON STABILITY3, 10 IMOD/IMMON IBMON Compliance Voltage SUPPLY ICC11 VCC (with Respect to GND)12
1 2 3
Min 76 85 92
Typ 98 98 100 42
Max 112 115 108 5 1.3
Unit A/A A/A A/A % A/A V mA V
Conditions/Comments 2 mA < IBIAS < 11 mA 11 mA < IBIAS < 50 mA 50 mA < IBIAS < 100 mA 10 mA < IBIAS < 100 mA
0 31 3.3
When IBIAS = IMOD = 0 mA
3.0
3.6
Temperature range is from -40C to +85C. Measured into a single-ended 15 load (22 resistor in parallel with digital scope 50 input) using a 1111111100000000 pattern at 2.5 Gbps, shown in Figure 2. Guaranteed by design and characterization. Not production tested. 4 Measured into a single-ended 15 load using a K28.5 pattern at 2.5 Gbps, shown in Figure 2. 5 Measured into a differential 30 (43 differential resistor in parallel with a digital scope of 50 input) load using a 1111111100000000 pattern at 4.25 Gbps, as shown in Figure 3. 6 Measured into a differential 30 load using a K28.5 pattern at 4.25 Gbps, as shown in Figure 3. 7 Measured into a differential 30 load using a K28.5 pattern at 2.7 Gbps, as shown in Figure 3. 8 When the voltage on DATAP is greater than the voltage on DATAN, the modulation current flows into the IMODP pin. 9 Guaranteed by design. Not production tested. 10 IBIAS/IBMON ratio stability is defined in SFF-8472 Revision 9 over temperature and supply variation. 11 See the ICC minimum for power calculation in the Power Consumption section. 12 All VCC pins should be shorted together.
VCC
VCC L
ADN2873
IMODP
R 22
C
BIAS TEE 80kHz 27GHz
Figure 2. High Speed Electrical Test Single-Ended Output Circuit
BIAS TEE 80kHz 27GHz VCC
L IMODN R 43
C TO HIGH SPEED DIGITAL OSCILLOSCOPE 50 DIFFERENTIAL INPUT C
ADN2873
IMODP
L
VCC BIAS TEE 80kHz 27GHz
07493-003
Figure 3. High Speed Electrical Test Differential Output Circuit
Rev. 0 | Page 4 of 20
07493-002
TO HIGH SPEED DIGITAL OSCILLOSCOPE 50 INPUT
ADN2873
SFP TIMING SPECIFICATIONS
Table 2.
Parameter ALS Assert Time ALS Negate Time1 Time to Initialize, Including Reset of FAIL1 FAIL Assert Time ALS to Reset Time
1
Symbol t_off t_on t_init t_fault t_reset
Min
Typ 1 0.15 25
Max 5 0.4 275 100 5
Unit s ms ms s s
Conditions/Comments Time for the rising edge of ALS (Tx_DISABLE) to when the bias current falls below 10% of nominal Time for the falling edge of ALS to when the modulation current rises above 90% of nominal From power-on or negation of FAIL using ALS Time to fault to FAIL on Time Tx_DISABLE must be held high to reset Tx_FAULT
Guaranteed by design and characterization. Not production tested.
VSE DATAP DATAN
DATAP - DATAN
07493-004
0V
V p-p DIFF = 2 x VSE
Figure 4. Signal Level Definition
SFP MODULE
1H VCC_Tx 0.1F 0.1F 10F
07493-005
3.3V
SFP HOST BOARD
Figure 5. Recommended SFP Supply
Rev. 0 | Page 5 of 20
ADN2873 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter VCC to GND IMODN, IMODP All Other Pins Junction Temperature Operating Temperature Range, Industrial Storage Temperature Range Junction Temperature (TJ max) Power Dissipation1 JA Thermal Impedance2 JC Thermal Impedance Lead Temperature (Soldering, 10 sec)
1
Rating 4.2 V -0.3 V to +4.8 V -0.3 to +3.9 V 150C -40C to +85C -65C to +150C 125C (TJ max - TA)/JA W 30C/W 29.5C/W 300C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Power consumption equations are provided in the Power Consumption section. 2 JA is defined when the part is soldered on a four-layer board.
Rev. 0 | Page 6 of 20
ADN2873 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IBIAS GND IMODN IMODP VCC GND
CCBIAS PAVSET GND VCC PAVREF RPAV 1 2 3 4 5 6
24 23 22 21 20 19
PIN 1 INDICATOR
ADN2873
TOP VIEW (Not to Scale)
18 17 16 15 14 13
FAIL IBMON VCC ERREF IMMON ERSET
NOTES 1. NC = NO CONNECT. 2. THE LFCSP HAS AN EXPOSED PADDLE THAT MUST BE CONNECTED TO GND.
NC PAVCAP GND DATAP DATAN ALS
7 8 9 10 11 12
Figure 6. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Mnemonic CCBIAS PAVSET GND VCC PAVREF RPAV NC PAVCAP GND DATAP DATAN ALS ERSET IMMON ERREF VCC IBMON FAIL GND VCC IMODP IMODN GND IBIAS Description Not Used (Internally Connected to VCC) Average Optical Power Set Pin Supply Ground Supply Voltage Reference Voltage Input for Average Optical Power Control Average Power Resistor when Using PAVREF No Connect Average Power Loop Capacitor Supply Ground Data, Positive Differential Input Data, Negative Differential Input Automatic Laser Shutdown Extinction Ratio Set Pin Modulation Current Monitor Current Source Reference Voltage Input for Extinction Ratio Control Supply Voltage Bias Current Monitor Current Source FAIL Alarm Output Supply Ground Supply Voltage Modulation Current Positive Output (Current Sink), Connect to Laser Diode Modulation Current Negative Output (Current Sink) Supply Ground Laser Diode Bias (Current Sink to Ground)
Rev. 0 | Page 7 of 20
07493-006
ADN2873 TYPICAL PERFORMANCE CHARACTERISTICS
SINGLE-ENDED OUTPUT
These performance characteristics were measured using the high speed electrical single-ended output circuit shown in Figure 2.
90 1.2
1.0 RANDOM JITTER (rms)
07493-012
60 RISE TIME (ps)
0.8
0.6
30
0.4
0.2
0
20
40
60
80
100
0
20
40
60
80
100
MODULATION CURRENT (mA)
MODULATION CURRENT (mA)
Figure 7. Rise Time vs. Modulation Current, IIBIAS = 20 mA
80
Figure 9. Random Jitter vs. Modulation Current, IIBIAS = 20 mA
45 40
60 FALL TIME (ps)
DETERMINISTIC JITTER (ps)
35 30 25 20 15 10 5
40
20
07493-013
0
20
40
60
80
100
40
60
80
100
MODULATION CURRENT (mA)
MODULATION CURRENT (mA)
Figure 8. Fall Time vs. Modulation Current, IIBIAS = 20 mA
Figure 10. Deterministic Jitter at 2.488 Gbps vs. Modulation Current, IIBIAS = 20 mA
Rev. 0 | Page 8 of 20
07493-015
0
0 20
07493-014
0
0
ADN2873
DIFFERENTIAL OUTPUT
These performance characteristics were measured using the high speed electrical differential output circuit shown in Figure 3.
90
1.2
1.0
RANDOM JITTER (rms)
07493-016
RISE TIME (ps)
60
0.8
0.6
30
0.4
0.2
0
20
40
60
80
100
0
20
40
60
80
100
MODULATION CURRENT (mA)
MODULATION CURRENT (mA)
Figure 11. Rise Time vs. Modulation Current, IIBIAS = 20 mA
80
Figure 13. Random Jitter vs. Modulation Current, IIBIAS = 20 mA
40 35
60
DETERMINISTIC JITTER (ps)
30 25 20 15 10 5
FALL TIME (ps)
40
20
0
20
40
60
80
100
MODULATION CURRENT (mA)
MODULATION CURRENT (mA)
Figure 12. Fall Time vs. Modulation Current, IIBIAS = 20 mA
Figure 14. Deterministic Jitter at 4.25 Gbps vs. Modulation Current, IIBIAS = 20 mA
Rev. 0 | Page 9 of 20
07493-019
0
20
40
60
80
100
07493-017
0
0
07493-018
0
0
ADN2873
PERFORMANCE CHARACTERISTICS
240 220
TOTAL SUPPLY CURRENT (mA)
40 38 IIBIAS = 90mA
SUPPLY CURRENT (I CC)
100 180 160 140 120 100 80 60
36 34 32 30 28 26 24 22
07493-020
IIBIAS = 40mA
IIBIAS = 20mA IIBIAS = 10mA
0
10
20
40
60
80
100
-40
25 TEMPERATURE (C)
85
MODULATION CURRENT (mA)
Figure 15. Total Supply Current vs. Modulation Current Total Supply Current = IVCC + IIBIAS + IIMOD
120 115
Figure 18. Supply Current (ICC) vs. Temperature with ALS Asserted, IIBIAS = 11 mA
55
50
110 IIBIAS/IIBMON GAIN 105 100 95 90
35
IIMOD/IIMMON GAIN
45
40
85 80
30 -50
07493-021
-40
25 TEMPERATURE (C)
85
-30
-10
10
30
50
70
90
110
TEMPERATURE (C)
Figure 16. IIBIAS/IIBMON Gain vs. Temperature, IIBIAS = 11 mA
Figure 19. IIMOD/IIMMON Gain vs. Temperature, IIMOD = 30 mA
OC48 PRBS31 DATA TRANSMISSION
t_OFF LESS THAN 1s
TRANSMISSION
ALS
07493-022
ALS
t_ON
07493-025
Figure 17. ALS Assert Time, 5 s/DIV
Figure 20. ALS Negate Time, 50 s/DIV
Rev. 0 | Page 10 of 20
07493-024
07493-023
40
20
ADN2873
TRANSMISSION ON FAIL ASSERTED
FAULT FORCED ON PAVSET POWER SUPPLY TURNED ON
07493-026 07493-027
Figure 21. FAIL Assert Time,1 s/DIV
Figure 22. Time to Initialize, Including Reset, 40 ms/DIV
Rev. 0 | Page 11 of 20
ADN2873 OPTICAL WAVEFORMS
VCC = 3.3 V and TA = 25C, unless otherwise noted. Note that there was no change to PAVCAP and ERCAP values when different data rates were tested. Figure 23, Figure 24, and Figure 25 show multirate performance using the low cost Fabry Perot TOSA NEC NX7315UA; Figure 26 and Figure 27 show performance over temperature using the DFB TOSA Sumitomo SLT2486.
(ACQ LIMIT TEST) WAVEFORMS 1000 (ACQ LIMIT TEST) WAVEFORMS 1001
07493-007
Figure 23. Optical Eye 2.488 Gbps, 65 ps/DIV, PRBS 231 - 1 PAV = -4.5 dBm, ER = 9 dB, Mask Margin 25%
(ACQ LIMIT TEST) WAVEFORMS 1000
Figure 26. Optical Eye 2.488 Gbps, 65 ps/DIV, PRBS 231 - 1 PAV = 0 dBm, ER = 9 dB, Mask Margin 22%, TA = 25C
(ACQ LIMIT TEST) WAVEFORMS 1001
07493-008
Figure 24. Optical Eye 622 Mbps, 264 ps/DIV, PRBS 231 - 1 PAV = -4.5 dBm, ER = 9 dB, Mask Margin 50%
(ACQ LIMIT TEST) WAVEFORMS 1000
Figure 27. Optical Eye 2.488 Gbps, 65 ps/DIV, PRBS 231 - 1 PAV = -0.2 dBm, ER = 8.96 dB, Mask Margin 21%, TA = 85C
Figure 25. Optical Eye 155 Mbps,1.078 ns/DIV, PRBS 231 - 1 PAV = -4.5 dBm, ER = 9 dB, Mask Margin 50%
07493-009
Rev. 0 | Page 12 of 20
07493-011
07493-010
ADN2873 THEORY OF OPERATION
Laser diodes have a current-in to light-out transfer function, as shown in Figure 28. Two key characteristics of this transfer function are the threshold current, ITH, and the laser slope in the linear region beyond the threshold current, referred to as the slope efficiency, LI.
ER =
OPTICAL POWER
CONTROL METHODS
The ADN2873 has two methods for setting the average power (PAV) and ER. The laser optical output average power and extinction ratio are configurable by using the voltage setting or the resistor setting. In voltage setting mode, a microcontroller DAC can drive the PAVREF and ERREF pins with programmable voltages. Alternatively, in resistor setting mode, the resistor divider or potentiometers can set proper voltages at the PAVSET and ERSET pins. Refer to Figure 29 and Figure 30 for details.
P1
P1 PO P1 + PO PAV = 2
PAV I PO ITH
P P I
07493-028
VOLTAGE SETPOINT CALIBRATION
LI =
CURRENT
The ADN2873 allows interface to a microcontroller for both control and monitoring (see Figure 29). The average power and extinction ratio can be set using the microcontroller DACs to provide controlled reference voltages, PAVREF and ERREF. PAVREF = PAV x RSP x RPAV (V)
Figure 28. Laser Transfer Function
LASER CONTROL
Typically, laser threshold current and slope efficiency are both functions of temperature. For FP-type and/or DFB-type lasers, the threshold current increases and the slope efficiency decreases with increasing temperature. In addition, these parameters vary as the laser ages. To maintain a constant optical average power and a constant optical extinction ratio over temperature and laser lifetime, it is necessary to vary the applied electrical bias current and modulation current to compensate for the changing LI characteristics of the laser.
ERREF =
I MOD x R ERSET 100
(V)
where: PAV is the laser optical average power output required. RSP is the optical responsivity (in amperes per watt). RPAV = RERSET = 1 k. IMOD is the modulation current. In voltage setpoint mode, RPAV and RERSET must be 1 k resistors with a 1% tolerance and a temperature coefficient of 50 ppm/C.
Average Power Control Loop (APCL)
The APCL compensates for changes in ITH and LI by varying IBIAS. Average power control is performed by measuring the monitor photodiode (MPD) current, IMPD. This current is bandwidth limited by the MPD. This is not a problem because the APCL is required to respond to the average current from the MPD.
Power-On Sequence in Voltage Setpoint Mode
During power-up, an initial sequence allows 25 ms before enabling the alarms. Therefore, the user must ensure that the voltages applied to PAVREF and ERREF are stabilized within 20 ms after ramp-up of the power supply. If supplying the PAVREF and ERREF voltages after the 25 ms, the alarms and FAIL circuitry kick in before the voltages are stabilized to PAVREF and ERREF, which causes an unexpected failure.
Extinction Ratio (ER) Control
ER control is implemented by adjusting the modulation current. Temperature calibration is required to adjust the modulation current to compensate for variations of the laser characteristics with temperature.
Rev. 0 | Page 13 of 20
ADN2873
VCC Tx_DISABLE Tx_FAULT VCC MPD FAIL ALS VCC VCC L IMODN R IMODP DATAP ANALOG DEVICES MICROCONTROLLER DAC ADC PAVSET PAVREF RPAV 1k DAC GND ERREF ERSET 1k GND VCC GND IBMON IMMON x100 IMOD CCBIAS CONTROL 100 IBIAS DATAN VCC RZ LASER VCC
ADN2873
PAVCAP GND
07493-029
NC
1k GND
470 GND
Figure 29. Using Microconverter Voltage Setpoint Calibration and Monitoring
VCC
VCC
VCC L VCC LASER
FAIL VCC MPD RPAV PAVSET VCC PAVREF
ALS
IMODN
R IMODP
DATAP 100 IBIAS DATAN VCC RZ
CONTROL
GND
VCC ERREF ERSET VREF
x100 IMOD CCBIAS
ADN2873
GND VCC GND IBMON 1k GND IMMON 470 GND PAVCAP GND NC
Figure 30. Using Resistor Setpoint Calibration of Average Power and Extinction Ratio
Rev. 0 | Page 14 of 20
07493-030
ADN2873
RESISTOR SETPOINT CALIBRATION
In resistor setpoint calibration, the PAVREF, ERREF, and RPAV pins must all be tied to VCC. The average power and extinction ratio can be set using the PAVSET and ERSET pins, respectively. A resistor is placed between the pin and GND to set the current flowing in each pin, as shown in Figure 30. The ADN2873 ensures that both PAVSET and ERSET are kept 1.23 V above GND. The PAVSET and ERSET resistors are given by
R PAVSET = 1.2 V PAV x RSP
Method 2: Measuring IMPD Across a Sense Resistor
The second method has the advantage of providing a valid IMPD reading at all times but has the disadvantage of requiring a differential measurement across a sense resistor directly in series with the IMPD. As shown in Figure 32, a small resistor, Rx, is placed in series with the IMPD. If the laser used in the design has a pinout where the monitor photodiode cathode and the lasers anode are not connected, a sense resistor, Rx, can be placed in series with the photodiode cathode and VCC, as shown in Figure 33. When choosing the value of the resistor, the user must take into account the expected IMPD value in normal operation. The resistor must be large enough to make a significant signal for the buffered ADC to read, but small enough not to cause a significant voltage reduction across the photodiode. The voltage across the sense resistor should not exceed 250 mV when the laser is in normal operation. It is recommended that a 10 pF capacitor be placed in parallel with the sense resistor.
VCC
(k)
RERSET =
1.2 V x 100 IMOD
(k)
where: PAV is the average power required (mW).RSP is the optical responsivity (in mA/mW). IMOD is the modulation current required (mA).
Power-On Sequence in Resistor Setpoint Mode
Note that during power-up, the ADN2873 starts an initial process sequence that allows 25 ms before enabling the device alarms. The resistors connected to the PAVSET and ERSET pins should be stable within 20 ms after turning on the power supply. The ADN2873 alarm may kick in and assert FAIL, provided the PAVSET and ERSET resistors are stabilized 20 ms after turning on the power supply.
PHOTODIODE
LD
MICROCONVERTER ADC DIFFERENTIAL INPUT
200 Rx PAVSET
10pF
IMPD MONITORING
IMPD monitoring can be implemented for voltage setpoint and resistor setpoint as described in the following sections.
ADN2873
Figure 32. Differential Measurement of IMPD Across a Sense Resistor
VCC VCC
Voltage Setpoint
In voltage setpoint calibration, two methods can be used for IMPD monitoring: measuring voltage at RPAV and measuring IMPD across a sense resistor.
MICROCONVERTER ADC INPUT
200 Rx
LD
PHOTODIODE PAVSET
Method 1: Measuring Voltage at RPAV
The IMPD current is equal to the voltage at RPAV divided by the value of RPAV (see Figure 31) as long as the laser is on and is being controlled by the control loop. This method does not provide a valid IMPD reading when the laser is in shutdown or fail mode. A microconverter-buffered ADC input can be connected to RPAV to make this measurement. No decoupling or filter capacitors should be placed on the RPAV node because this can disturb the control loop.
VCC PHOTODIODE PAVSET
ADN2873
Figure 33. Single Measurement of IMPD Across a Sense Resistor
Resistor Setpoint
In resistor setpoint calibration, the current through the resistor from PAVSET to GND is the IMPD current. The recommended method for measuring the IMPD current is to place a small resistor in series with the PAVSET resistor (or potentiometer) and measure the voltage across this resistor, as shown in Figure 34. The IMPD current is then equal to this voltage divided by the value of resistor used. In resistor setpoint calibration, PAVSET is held to 1.2 V nominal; it is recommended that the sense resistor be selected so that the voltage across the sense resistor does not exceed 250 mV.
ADN2873
MICROCONVERTER ADC INPUT R 1k RPAV
Figure 31. Single Measurement of IMPD at RPAV in Voltage Setpoint Mode
Rev. 0 | Page 15 of 20
07493-031
07493-033
07493-032
ADN2873
VCC PHOTODIODE PAVSET
Power consumption can be calculated as
ICC = ICC min + 0.3 IMOD P = VCC x ICC + (IBIAS x VBIAS_PIN) + IMOD (VMODP_PIN + VMODN_PIN)/2 TDIE = TAMBIENT + JA x P
ADN2873
R
Figure 34. Recommended Method of IMPD Measurement Across a Sense Resistor in Resistor Setting Mode
LOOP BANDWIDTH SELECTION
To ensure that the ADN2873 control loop has sufficient bandwidth, the average power loop capacitor (PAVCAP) is calculated using the slope efficiency of the laser (watts/amps) and the average power required. For resistor setpoint control,
PAVCAP = 3.2 x 10 -6 x LI PAV
07493-034
MICROCONVERTER ADC INPUT
Thus, the maximum combination of IBIAS + IMOD must be calculated, where: ICC min = 32 mA, the typical value of ICC provided in Table 1 with IBIAS = IMOD = 0. TDIE is the die temperature. VBIAS_PIN is the voltage at the IBIAS pin. VMODP_PIN is the voltage at the IMODP pin. VMODN_PIN is the voltage at the IMODN pin. TAMBIENT is the ambient temperature.
AUTOMATIC LASER SHUTDOWN (TX_DISABLE)
ALS (TX_DISABLE) is an input that is used to shut down the optical output of the transmitter. The ALS pin is pulled up internally with a 6 k resistor and conforms to SFP MSA specifications. When ALS is logic high or when open, both the bias and modulation currents are turned off. If an alarm has been triggered and the bias and modulation currents are turned off, ALS can be brought high and then low to clear the alarm.
(Farad)
For voltage setpoint control,
PAVCAP = 1.28 x 10 -6 x LI PAV
(Farad)
where: LI is the typical slope efficiency at 25C of a batch of lasers that PAV is the average power required (mW). are used in a design (mW/mA). LI can be calculated as
LI = P1 - P0 I MOD
BIAS AND MODULATION MONITOR CURRENTS
IBMON and IMMON are current-controlled current sources that mirror a ratio of the bias and modulation current. The monitor bias current, IBMON, and the monitor modulation current, IMMON, should both be connected to ground through a resistor to provide a voltage proportional to the bias current and modulation current, respectively. When using a microcontroller, the voltage developed across these resistors can be connected to two of the ADC channels, making a digital representation of the bias and modulation current available.
(mW/mA)
where: P1 is the optical power (mW) at the one level. P0 is the optical power (mW) at the zero level. The capacitor value equation is used to obtain a centered value for the particular type of laser that is used in a design and an average power setting. The laser LI can vary by a factor of 7 between different physical lasers of the same type and across temperatures without the need to recalculate the PAVCAP value. This capacitor is placed between the PAVCAP pin and ground. It is important that the capacitor is a low leakage, multilayer ceramic type with an insulation resistance greater than 100 G or a time constant of 1000 sec, whichever is less. Pick a standard off-the-shelf capacitor value such that the actual capacitance is within 30% of the calculated value after the capacitor's own tolerance is taken into account.
IBIAS PIN
The ADN2873 IBIAS pin has one on-chip, 800 pull-up resistor. The current sink from this resistor is VIBIAS dependent.
I UP = VCC - V IBIAS 0. 8 (mA)
where VIBIAS is the voltage measured at the IBIAS pin after setup of one laser bias current, IBIAS. Usually, when set up, a maximum laser bias current of 100 mA results in a VIBIAS to about 1.2 V. In a worst-case scenario, VCC = 3.6 V, VIBIAS = 1.2 V, and IUP (the current bypass through the 800 resistor) 3 mA. This on-chip resistor damps out the low frequency oscillation observed from some inexpensive lasers. If the on-chip resistance does not provide enough damping, one external RZ (see Figure 35) may be necessary.
POWER CONSUMPTION
The ADN2873 die temperature must be kept below 125C. The LFCSP has an exposed paddle, which should be connected so that it is at the same potential as the ADN2873 GND pins.
Rev. 0 | Page 16 of 20
ADN2873
DATA INPUTS
Data inputs should be ac-coupled (10 nF capacitors are recommended) and are terminated via a 100 internal resistor between the DATAP and DATAN pins. A high impedance circuit sets the common-mode voltage and is designed to allow maximum input voltage headroom over temperature. It is necessary to use ac-coupling to eliminate the need for matching the common-mode voltages of the data source and the ADN2873 data input pins. transmission line values can be used, with some modification of the component values. In Figure 35, the R and C snubber values 24 and 2.2 pF, respectively, represent a starting point and must be tuned for the particular model of laser being used. RP, the pull-up resistor, is in series with a very small (0.5 nH) inductor. In some cases, an inductor is not required or can be accommodated with deliberate parasitic inductance, such as a thin trace or a via placed on the PC board. Care should be taken to mount the laser as close as possible to the PC board, minimizing the exposed lead length between the laser can and the edge of the board. The axial lead of a coax laser is very inductive (approximately 1 nH per mm). Long exposed leads result in slower edge rates and reduced eye margin. Recommended component layouts and Gerber files are available by contacting sales at Analog Devices. Note that the circuit in Figure 35 can supply up to 56 mA of modulation current to the laser, sufficient for most lasers available today. Higher currents can be accommodated by changing transmission lines and backmatch values; contact sales for recommendations. This interface circuit is not recommended for butterfly-style lasers or other lasers with 25 characteristic impedance. Instead, a 25 transmission line and inductive (instead of resistive) pull-up is recommended. The ADN2873 single-ended application shown in Figure 35 is recommended for use up to 2.7 Gbps. From 2.7 Gbps to 4.25 Gbps, a differential drive is recommended when driving VCSELs or lasers that have slow fall times. Differential drive can be implemented by adding a few extra components. A possible implementation is shown in Figure 36. The bias and modulation currents that are programmed into the ADN2873 need to be larger than the bias and modulation current required at the laser due to the laser ac coupling interface and because some modulation current flows in the pull-up resistors, R1 and R2. In Figure 35 and Figure 36, Resistor RZ is required to achieve optimum eye quality. The recommended RZ value is approximately 500 ~ 800 . The interface circuit needs a special modification to support HDTV pathological test patterns. Contact sales at Analog Devices for HDTV support.
L4 = BLM18HG601SN1D
LASER DIODE INTERFACING
Figure 35 shows the recommended circuit for interfacing the ADN2873 to most TO-can or coax lasers. Uncooled DFB and FP lasers typically have impedances of 5 to 7 and have axial leads. The circuit shown works over the full range of data rates from 155 Mbps to 3.3 Gbps, including multirate operation (without changes to PAVCAP and ERCAP values); see Figure 23, Figure 24, and Figure 25 for multirate performance examples. Coax lasers have special characteristics that make them difficult to interface to. They tend to have higher inductance and their impedance is not well controlled. The circuit in Figure 35 operates by deliberately misterminating the transmission line at the laser side while providing a very high quality matching network at the driver side. The impedance of the driver side matching network is very flat in the designed frequency range and enables multirate operation. A series damping resistor should not be used.
VCC L (0.5nH) RP 24 IMODP C 100nF Tx LINE 30 R 24 C 2.2pF
07493-035
VCC
ADN2873
IBIAS
VCC
Tx LINE 30 RZ
L
BLM18HG601SN1D
Figure 35. Recommended Interface for ADN2873 AC Coupling
The 30 transmission line used is a compromise between the drive current required and the total power consumed. Other
VCC L1 = 0.5nH
R1 = 15 IMODN
C1 = C2 = 100nF
L3 = 4.7nH C3 SNUBBER
TO-CAN/VCSEL
ADN2873
IMODP IBIAS
20 TRANSMISSION LINES R3
LIGHT
R2 = 15
L2 = 0.5nH VCC VCC RZ
L6 = BLM18HG601SN1D
SNUBBER SETTINGS: 40 AND 1.5pF, NOT OPTIMIZED, OPTIMIZATION SHOULD CONSIDER THE PARASITIC OF THE INTERFACE CIRCUITRY.
Figure 36. Recommended Differential Drive Circuit
Rev. 0 | Page 17 of 20
07493-036
ADN2873
ALARMS
The ADN2873 has a latched, active high monitoring alarm (FAIL). The FAIL alarm output is open drain in conformance with SFP MSA specification requirements. The ADN2873 has a three-fold alarm system that covers
* *
*
Use of a bias current that is higher than expected, likely as a result of laser aging Out-of-bounds average voltage at the monitor photodiode (MPD) input, indicating an excessive amount of laser power or a broken loop Undervoltage in the IBIAS node (laser diode cathode) that would increase the laser power
activated when the single-point alarms in Table 5 occur. The circuit in Figure 37 can be used to indicate that FAIL has been activated while allowing the bias and modulation currents to remain on. The VBE of the transistor clamps the FAIL voltage to below 1.3 V, disabling the automatic shutdown of bias and modulation currents. If an alarm has triggered and FAIL is activated, ALS can be brought high and then low to clear the alarm.
VCC LED D1 R1 10k FAIL R2 330 Q1 NPN
07493-037
The bias current alarm trip point is set by selecting the value of resistor on the IBMON pin to GND. The alarm is triggered when the voltage on the IBMON pin goes above 1.2 V. FAIL is
ADN2873
Figure 37. FAIL Indication Circuit
Table 5. ADN2873 Single-Point Alarms
Alarm Type Bias Current MPD Current Crucial Nodes Mnemonic IBMON PAVSET ERREF (the ERRREF designed is tied to VCC in resistor setting mode) IBIAS Overvoltage or Short to VCC Condition Alarm if >1.2 V typical (10% tolerance) Alarm if >2.0 V Alarm if shorted to VCC (the alarm is valid for voltage setting mode only) Ignore Undervoltage or Short to GND Condition Ignore Alarm if <0. 4V Ignore Alarm if shorted to GND
Table 6. ADN2873 Response to Various Single-Point Faults in AC-Coupled Configuration (as shown in Figure 35 and Figure 36)
Pin PAVSET PAVREF Short to VCC Fault state occurs Voltage mode: fault state occurs Resistor mode: tied to VCC Voltage mode: fault state occurs Resistor mode: tied to VCC Fault state occurs Does not increase laser average power Does not increase laser average power Output currents shut off Does not increase laser average power Does not affect laser power Voltage mode: fault state occurs Resistor mode: tied to VCC Fault state occurs Fault state occurs Does not increase laser average power Does not increase laser average power Fault state occurs Short to GND Fault state occurs Fault state occurs Open Fault state occurs Fault state occurs Circuit designed to tie to VCC in resistor setting mode, so no open case Voltage mode: fault state occurs Resistor mode: does not increase average power Fault state occurs Does not increase laser average power Does not increase laser average power Output currents shut off Does not increase laser average power Does not increase laser average power Does not increase laser average power
RPAV
Fault state occurs
PAVCAP DATAP DATAN ALS ERSET IMMON ERREF
IBMON FAIL IMODP IMODN IBIAS
Fault state occurs Does not increase laser average power Does not increase laser average power Normal currents Does not increase laser average power Does not increase laser average power Voltage mode: does not increase average power Resistor mode: fault state occurs Does not increase laser average power Does not increase laser average power Does not increase laser average power Does not increase laser average power Fault state occurs
Does not increase laser average power Does not increase laser average power Does not increase laser average power Does not increase laser power Fault state occurs
Rev. 0 | Page 18 of 20
ADN2873 OUTLINE DIMENSIONS
4.00 BSC SQ 0.60 MAX 0.60 MAX 0.50 BSC 0.50 0.40 0.30 1.00 0.85 0.80 12 MAX 0.80 MAX 0.65 TYP
19 18 EXPOSED PAD 24 1
PIN 1 INDICATOR *2.45 2.30 SQ 2.15
6
PIN 1 INDICATOR
TOP VIEW
3.75 BSC SQ
(BO TTOMVIEW)
13 12
7
0.23 MIN 2.50 REF
0.05 MAX 0.02 NOM 0.20 REF COPLANARITY 0.08
SEATING PLANE
0.30 0.23 0.18
*COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2 EXCEPT FOR EXPOSED PAD DIMENSION
Figure 38. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Body, Very Thin Quad (CP-24-2) Dimensions shown in millimeters
ORDERING GUIDE
Model ADN2873ACPZ1 ADN2873ACPZ-RL1 ADN2873ACPZ-RL71
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C
Package Description 24-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 24-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 24-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
Package Option CP-24-2 CP-24-2 CP-24-2
Z = RoHS Compliant Part.
Rev. 0 | Page 19 of 20
ADN2873 NOTES
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07493-0-6/08(0)
Rev. 0 | Page 20 of 20

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